FIELD OF THE INVENTION
The invention relates to a semiconductor structure for an MOS transistor with a substrate, a gate oxide and a polysilicon layer lying above it. Furthermore, the invention relates to a method for fabricating such a semiconductor structure.
Integrated MOS circuits, and in particular CMOS circuits, are fabricated with various methods in which the well dopants are generally introduced and implanted by temperature treatment. Then, isolation areas are produced by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). After the isolation areas have been produced, a gate oxide is grown on the active areas by thermal oxidation and covered with a gate electrode which is preferably composed of polysilicon. The polysilicon is structured with a resist mask and reactive ion etching (RIE). The etching must thereby be sufficiently selective with respect to the gate oxide underneath, so that the substrate is not attacked during the etching. The production of the integrated circuit is then continued in a known manner.
Two significant problems, amongst others, arise during the fabrication of such integrated MOS transistors, and in particular of CMOS transistors. One problem relates to the quality of the gate oxide and the other to the topology during the structuring of the gate electrode. The quality of the gate oxide is essentially characterized by the defect density and the breakdown field strength. As the number of process steps involved in the production of the gate oxide increases, the quality of the gate oxide becomes worse, since each preceding process step increases the defect density and the surface becomes increasingly uneven. Therefore, it is desirable to produce the gate oxide as early as possible, i.e., during one of the first process steps, and to cover it with a gate electrode.
When the insulation of integrated CMOS circuits is produced by means of the local oxidation technique (LOCOS), for example, there is always a topology step at the junction between the active region and the insulation area. That topology step is of the order of magnitude of the thickness of the gate electrode, and is thus in the range of approximately 0.5 .mu.m. As a result of different resist thicknesses and reflections at the field oxide edge, this has a disadvantageous effect on the dimensional accuracy during the structuring of the gate electrode. Furthermore, a spacer is formed at the field oxide step, so that the gate electrode is significantly thicker at this point than in the other areas. The greater thickness at this point must be allowed for by means of a longer etching time. However, on the other hand the etching must not continue through the extremely thin gate oxide and into the substrate. For a given level of the topology step at the field oxide edge this results in a very high etching selectivity and/or a correspondingly thick gate oxide.